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| TH3122 K-Bus Transceiver with integrated Voltage Regulator Features and Benefits K-Bus Transceiver: PNP-open emitter driver with slew rate control and current limitation BUS input voltage -24V ... 30V (independently of VS) ISO 9141 and ODBII compliant Possibility of BUS wake up Operating voltage VS = 5.5 ... 16 V Very low standby current consumption <100 A in normal mode (< 50 A in sleep mode) Linear low drop voltage regulator: Output voltage 5V 2% Output current max. 100mA Output current limitation Overtemperature shutdown Pin Diagram SOIC16 VS EN VTR GND GND BUS SI SO 1 16 VCC SENSE RESET GND GND TxD RxD SEN/STA 2 15 3 14 4 13 TH3122 5 12 6 11 7 10 8 9 Configurable reset time (15ms/100ms) and reset threshold voltage (3.15V / 4.65V) Low voltage detection at VS Wake-up by K-BUS traffic and start-up capable independent of EN voltage level Universal comparator with an input voltage range -24V ... 30V and digital output Load dump protected (40V) Ordering Information Part No. TH3122 Temperature Code K ( -40C to 125C ) Package Code DF ( SOIC16, 300mil ) General Description The TH3122 consists of a low drop voltage regulator 5V/100mA and a K-Bus transceiver. The transceiver is suitable for K-Bus systems conform to ISO 9141. The combination of voltage regulator and bus transceiver in combination with the monitoring functions make it possible to develop simple, but powerful and cheap nodes in K-Bus systems. The wide output current area and the configurable reset time and reset voltage works together with many different microcontrollers. 3901003122 Rev 004 Page 1 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Functional Diagram VS Power Supply VCC Over Temp EN +5V 7.8V 6.8V +5V SENSE Reset-Logic VTR VTR-Logic RESET OSC Wake-up VthH VthL RxD BUS Bus-Logic pnp Control slew rate foldback +5V TxD SEN/STA SI VTHSI_H VTHSI_L SO Figure 1 - Block Diagram 3901003122 Rev 004 Page 2 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Functional Description The TH3122 consists of a voltage regulator 5V/100mA and a K-Bus transceiver, which is a bi-directional bus interface device for data transfer between K-Bus and the K-Bus protocol controller. to Wake-up Logic Also integrated into the transceiver are a voltage and time controlled reset management, power down, wake up function and a universal comparator for extended applications. tdebWake tdebBUS RxD POR VBAT POR VCC Controllogic Bit-Compare Constant-Low VthH VthL VCC pnpControl - slew rate - IB - foldback BUS TxD ESD VCC OSC Vref Biasing SENSE ESD Figure 2 - Block Diagram K-Bus Transceiver K-BUS Interface The BUS Interface builds the connection between the serial 5V bus line of the protocol controller and the 12V K-Bus line. The transceiver consists of a pnp-driver with slew rate control and fold-back characteristic and contains also in the receiver a high voltage comparator followed by a debouncing unit. electromagnetic emission of the bus line, the TH3122 has an integrated slew rate control. Receive Mode The data at the pin BUS will be transferred to the pin RxD. Short spikes on the bus signal are suppressed by the implemented debouncing circuit. BUS Transmit Mode During the transmission the data at the pin TxD will be transferred to the pin BUS. To minimize the < tdebH < tdebL SEN/STA RxD tdebH tdebL TxD Figure 4 - Receive Mode Pulse Diagram BUS Figure 3 - Transmit Mode Pulse Diagram 3901003122 Rev 004 Page 3 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Bit Compare If the signals at the pin TxD and the pin BUS within a specified time tbc are not identical, the transmission will be interrupted. If both signals at TxD and BUS are "High" within the time tena the transmission will be enabled. The bit-compare-function is active when the pin SEN/ STA is open (not overwritten). Using this pin as an input the transmission path can be overwritten (independent of bit-compare and constant-low function): SEN/STA="0" forcing the transmission path free SEN/STA="1" disable the transmission path Constant Low Switch Off A falling edge at pin TxD (from "1" to "0") starts the internal constant low timer (SEN/STA open). If the low level "0" is valid for the time tlow the transmission unit of the TH3122 will be disabled. The receive unit is still active. A high level "1" at TxD with a minimum pulse width of trec resets the constant low timer. Transmitting is not possible until TxD and BUS is High for the time tena. t < trec Figure 5 - Bit Compare Pulse Diagram SEN/STA The pin SEN/STA is bidirectional. Used as an output the pin indicates whether the transmit-path is enabled or disabled: SEN/STA ="0" transmission path is enabled SEN/STA ="1" transmission path is disabled TxD SEN/STA tlow tena Figure 6 - Constant Low Pulse Diagram Linear Regulator and Controlling Functions Regulator The TH3122 has an integrated linear regulator with an output voltage of 5V 2% and an output current of max. 100mA. The regulator is switched on or off with a signal on the EN pin or wakes up with a BUS signal. voltage level on the VTR pin (see table VTR Programming). After tRES a rising edge on the RESET output is generated (see figure 7 - Initialization). The regulator is active and can only be switched off with a falling edge on EN. The regulator remains with EN=high in active mode and therefore the VCC voltage is also active. Initialization The initialization is started if the power supply is switched on, or after the temperature limitation has switched off the regulator or in case of BUS traffic (wake up). If the VCC voltage level is higher than VRESEIN, the reset time tRES is started. This reset time is determined by the 3901003122 Rev 004 Page 4 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator VTR-Mode VS VRES VRES = VRES1 = 3.15V VRES = VRES2 = 4.65V VRES = VRES1 = 3.15V VRES = VRES2 = 4.65V tRes 100ms 100ms 15ms 15ms VTR = GND VTR = VCC VRESEIN VCC tRes VRES1/2 trr VTR with R 50k to GND VTR with R 50k to VCC RESET VTR-Programming The voltage on VTR input is read out if the voltage at this pin is higher than VRESEIN . This value defines the reset switch off voltage VRES. With the next oscillator cycle it switches on the pull up current source if VTR=low or the pull down current source if VTR=high. The sources are active for one oscillator cycle. The level changes during this procedure on VTR, which depends on the external pull up or pull down resistors control the reset time tRes Figure 7 - Initialization The input EN has an internal pull down resistor. If EN=high, the internal pull down current is switched off to minimize the quiescent current. RESET Output The RESET output is switched from low to high if VS is switched on and VCC>VRESEIN after the time tRES. If the voltage VCC drops below VRES1 or VRES2 then the RESET output is switched from high to low after the time trr has been reached. The voltage level for VRES1 and VRES2 and the corresponding times tRES can be programmed via the analogue input VTR. Temperature Limitation If the junction temperature 150C < Tj < 170C the over temperature recognition will be active and the regulator voltage and the BUS driver will be switched off. After Tj falls below 140C the TH3122 will be initialized, independently of the voltage levels on EN and BUS. The function of the TH3122 is possible between TAmax and the switch off temperature, but small parameter differences can appear. Wake up with BUS traffic If the regulator is put in standby mode it can be woken up with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of min. 45 s will switch on the regulator. After the BUS has woken up the regulator, it can only be switched off with a high level followed by a low level on the EN pin. Low Voltage Detection VS Low voltage on VS is monitored on SENSE output. If VS has reached the level of VS =6.8V then the SENSE output generates low level. The normal operating range is VS > 7.8V and the SENSE output generates a high level. Reset Programming on VTR With the VTR pin the reset switches off levels and delay time can be programmed. The voltage on VCC influences the reset function. Universal Comparator The TH3122 consist of a universal comparator for general use. The positive input of this comparator is connected to the pin SI. The input voltage range of SI is 0V...VS. The input voltage is compared with a fixed reference voltage at high or low level and the comparator output SO drives a 5V digital signal. 3901003122 Rev 004 Page 5 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Application Hints Operating during Disturbances The absence of VS ,VCC or GND connection or ground shift either alone or in any combination, do not influence or disturb the communication between other bus nodes. Regulator Circuitry The choice and dimension of the capacitor on VCC is determined by application point of view. Important parameters are the current difference on load changes and the maximum short time voltage drop. The VCC pin must be connected to a min. 2 F capacitor for stable operating of the regulator in the whole operating range. Undervoltage The reset unit secures the correct behavior of the driver during undervoltage. The inputs have pull-up or pulldown characteristics and have therefore defined voltage levels. With 4.5V VCC 5.25V the bus connection operates within the correct parameters . If VRES1 VCC 4.5V the TxD signal is transmitted to the bus. The receive mode is also active. If VCC < VRES1the bus driver is tristate. SENSE and SO output the correct signal if VCC > VRES . The specificated values of the input voltages on SO can't guaranteed. Short Circuit Proof All in- and outputs are short circuit proof to battery and ground. A thermal shut down circuit prevents VCC and BUS from any damage. Baud Rate The TH3122 has a maximum Baud rate of 9600 Baud (CBUS < 25nF, RPU > 400 ). Application Circuitry battery reverse diode TH3122 VS VCC EN SENSE VTR RESET GND GND GND GND BUS TxD SI RxD SO SEN/STA C +5V Port X.1 Reset VBat 100u 47n 33uH 6.8u TxD RxD BUS optional 10 82p Control Unit 100p Figure 8 - Application Circuit There should be used an LC-Filter to minimize the influence of EMI on the BUS lines. 3901003122 Rev 004 Page 6 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Reliable operation of the TH3122 is only specified within the limits shown in "Operating conditions". Operating Conditions Parameter Battery voltage Supply voltage Operating ambient temperature Junction temperature [1] Symbol VS VCC TA TJ Min 5.25 4.75 -40 Max 16 5.25 +125 +150 Unit V V C C Absolute Maximum Ratings Parameter Symbol Condition Min -1.0 Supply voltage at VS [2] VS T 1min T 500 ms Input voltage at pin BUS [2] -24 VINBUS T 500 ms -0.3 -0.3 -0.3 -25 -500 Internal limited [3] [4] 50 150 -55 150 Max 16 30 40 30 V 40 40 VS+0.3 VCC+0.3 25 500 V V V mA mA mW K/W C C V Unit Difference VS-VCC Input voltage at pin EN and SI Input voltage at pin VTR, TxD, SEN/STA, SO, RESET, SENSE Input current at pin EN, VTR, SI, SO, SEN/STA, TxD, RxD,RESET, SENSE Input current for short circuit of pin VS and VCC Power dissipation Thermal resistance from junction to ambient Junction temperature [4] Storage temperature VS-VCC VINENSI VIN IIN IShort P0 RTHJA TJ TSTG ______________________________ [1] [2] Junction temperature is defined in IEC 747-1 The current and voltage values are valid independent from each other. [3] The maximum power dissipation is defined by the ambient temperature and the thermal resistance. It can be calculated with P0 =(VS-VCC)*IVCC+PBUS. PBUS is the BUS driver output with normally 25 mW [4] see over temperature protection 3901003122 Rev 004 Page 7 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Static Characteristics (VS = 5.25 to 16V, VCC= 4.75 to 5.25V, TA = -40 to +125C, unless otherwise specified) Parameter Linear Regulator VCCn Output voltage VCC VCCt VCCh VCCI Supply current, normal mode" Supply current, sleep mode" ISnl ISsleep 5.5V VS 16V TA = 25C 5.5V VS 16V VSUP > 16V 3.3 V< VS< 5.5 V VEN = VS = 12V, Pins 8-11, 14-16 open VEN = 0V, VCC switched off VS 4.0V, IVCC = 25mA Drop-out voltage VD VS 4.0V, IVCC = 100mA VS 3.3V, IVCC = 20mA Output current VCC Current limitation VCC Load capacity Power-on-reset threshold "VCC on" Power-on-reset threshold "VCC off" VRES1 SENSE-Output VS - threshold low at SENSE VS - threshold high an SENSE Hysteresis SENSE Output voltage low Output voltage high Enable-Input EN Input voltage low Input voltage high Hysteresis Pull-down current EN Output RESET IOUT = 1 mA, VSUP > 5.5 V Output voltage low VOL Ipu 10 k RESET to VCC -500 -375 0.8 0.2 -250 V V A VENL VENH VENHYS IpdEN VEN > VENH VEN < VENL -0.3 2.5 100 1.8 70 4.0 100 7.5 130 1.75 VS +0.3 V V mV A A VSENL VSENH VSENHYS VOL VOH IOUT = 1mA IOUT = -1mA VCC-0.8 100 0.8 6.8 7.8 V V mV V V VTR=Low, VS > 0V 3.0 3.15 3.3 IVCC ILVCC Cload VRESEIN VRES2 VS 3.0V VS > 0V ESR 5 refered to VCC, VS > 4.6V VTR=High, VS > 0V 2 4.5 4.5 4.65 4.65 4.8 4.8 V 100 300 35 4.95 4.90 4.95 VS-VD 5.0 5.0 5.0 5.05 5.10 5.25 5.1 100 50 200 400 600 V V V V A A mV mV mV mA mA F V Symbol Condition Min Typ Max Unit Pull-up current 3901003122 Rev 004 Page 8 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Static Characteristics (continued) Parameter Comparator SI, SO Threshold low SI Threshold High SI Hysteresis Output voltage low at SO Pull-up current at SO Input VTR Threshold low Threshold high Output current low Output current high K-Bus-Interface Power-on-reset threshold Pull-up current TxD Pull-down current SEN/STA Pull-up current SEN/STA Input voltage low TxD, SEN/STA Input voltage high TxD, SEN/STA Input voltage low BUS Input voltage high BUS Hysteresis BUS VPOR Ipu IpdSEN IpuSEN VIL VIH VIL VIH VHYS 0 VBUS 40 V 0 VBUS 40 V Input restistance BUS RINBUS TA 125 C VBUS = -25V TA 125 C VS = 12V, SENSE = low IOUT = 40 mA VS = 12V, SENSE = low IOUT = 25 mA VBUS > 2.5V IOUT = 1 mA IOUT = -1mA VCC-0.8 40 60 1.2 V 1.0 100 0.8 mA V V 400 0.55 50 600 1500 0.75 0.45 VPOR =VRES1 3.0 -500 250 -500 3.15 -375 375 -375 3.3 -250 500 -250 0.25 V A A A VCC VCC VS VS mV VTRL VTRH IOL VCC > 3.3 V IOH -300 -230 -160 160 0.15 0.25 0.75 230 0.85 300 VCC VCC A A VIL VIH VHYS IOUT = 1 mA, VS > 5.5 V VOL Ipu 10 k SO to VCC, VCC > 3.3V -500 -375 30 0.8 0.4 -250 1.05 1.16 1.21 1.4 V V mV V V A Symbol Condition Min Typ Max Unit 1300 k Output voltage BUS VBUS Current limitation BUS Output voltage low RxD Output voltage high RxD ILIM VOL VOH 3901003122 Rev 004 Page 9 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Dynamic Characteristics (5.25V VS 16V, 4.75V VCC 5.25V, -40C TA 125C, unless otherwise specified) Parameter RESET Reset time Reset rising time K-Bus-Interface Slew rate BUS falling edge Slew rate BUS rising edge Symmetry of Slew rate BUS Debouncing time BUS Symmetry of debouncing BUS Propagation delay TxD -> RxD Symmetry of propagation delay TxD -> RxD Bit compare time BUS, SENSE, TxD Recovery time BUS, TxD Inhibit time for transmit BUS, TxD Constant low switch off BUS, TxD Oscillator frequency Debouncing time TxD Debouncing time EN Wake-up debouncing BUS Propagation delay SI -> SO Debouncing VS-SENSE dV/dTfall dV/dTrise dV/dTsym tdebBUS tdebsym tpd tpdsym tbc trec tena tlow fOSC tdeb tdeb tdebWake tpdcomp tdeb 35 30 0.92 3 8 0.6 200 25 4 10 17 45 90 11 25 52 50 1.33 6 12 1.0 High pulse or low pulse 1.5 2.8 -2.2 1.0 -1.6 1.6 -1.0 V/s 2.2 0.3 4.0 0.5 20 3.5 70 75 1.8 12 15 1.5 V/ s s s s s s s ms ms kHz s ns s s s tRes trr RVTR < 1 k RVTR > 45 k 70 10 3.0 100 15 6.5 140 20 10 ms ms s Symbol Condition Min Typ Max Unit 3901003122 Rev 004 Page 10 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Pin Description VS EN VTR GND GND BUS SI SO 1 16 VCC SENSE RESET GND GND TxD RxD SEN/STA 2 15 3 14 4 13 TH3122 5 12 6 11 7 10 8 9 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VS EN VTR GND GND BUS SI SO SEN/STA RxD TxD GND GND RESET SENSE VCC I/O Supply voltage I I Function Enable Input voltage regulator, HV-pull-down-Input, High-active Analogue Input - definition of reset time und Reset voltage level Ground Ground I/O I O I/O O I Bi-directional bus line Comparator Input, HV-Input 5V-Comparator Output Send status Receive Output, 5V-push-pull 5V-Transmit Input, pull-up-Input Ground Ground O O O 5V-output reset, active low 5V-output of VS-Monitoring Regulator output 5V/100mA 3901003122 Rev 004 Page 11 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Mechanical Specifications DF (SOIC16) Package Dimensions E H 123 D A1 e b A L Small Outline Integrated Circiut (SOIC), All Dimension in mm, coplanarity < 0.1 mm DF (SOIC 16, A1 0.10 0.30 300 mil) D min max 10.1 10.5 E 7.40 7.60 H 10.00 10.65 A 2.35 2.65 e 1.27 b 0.33 0.51 L 0.40 1.27 0 8 All Dimension in inch, coplanarity < 0.004" min max 0.398 0.413 0.291 0.299 0.394 0.419 0.093 0.104 0.004 0.012 0.050 0.013 0.020 0.016 0.050 0 8 3901003122 Rev 004 Page 12 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Assembly Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2) EIA/JEDEC JESD22-A113 Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2) CECC00802 Standard Method For The Specification of Surface Mounting Components (SMDs) of Assessed Quality EIA/JEDEC JESD22-B106 Resistance to soldering temperature for through-hole mounted devices EN60749-15 Resistance to soldering temperature for through-hole mounted devices MIL 883 Method 2003 / EIA/JEDEC JESD22-B102 Solderability For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD's is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Based on Melexis commitment to environmental responsibility, European legislation (Directive on the Restriction of the Use of Certain Hazardous substances, RoHS) and customer requests, Melexis has installed a roadmap to qualify their package families for lead free processes also. Various lead free generic qualifications are running, current results on request. For more information on Melexis lead free statement http://www.melexis.com/html/pdf/MLXleadfree-statement.pdf see quality page at our website: ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 3901003122 Rev 004 Page 13 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis' rendering of technical or other services. (c) 2002 Melexis NV. All rights reserved. For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: Phone: +32 13 67 04 95 E-mail: sales_europe@melexis.com All other locations: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com ISO/TS 16949 and ISO14001 Certified 3901003122 Rev 004 Page 14 Dec/04 |
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